Is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, RISC-V is provided under royalty-free open-source licenses. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available, and the instruction set is supported in several popular software toolchains.
Why be excited over RISC-V
Disruption is coming to the CPU industry. RISC-V is here to provide an open-source alternative to proprietary CPU instruction set architectures, providing the industry with a wider choice of chip designs with greater potential design flexibility. Established players are putting their support behind the ISA, helping to drive greater momentum to the ecosystem. For example, Google has announced that it will now support RISC-V as a Tier 1 platform for its Android operating system.
RISC is a computer architecture philosophy proposed in the 1980s as an alternative to the commercial architectures offered at the time by Intel, Motorola, and pretty much everyone else. Currently, the mobile and tablet market (and now some laptops) are dominated by ARM, ARM is a closed source ISA.
Being the fifth generation of a research project that started in 1980, RISC-V is a seasoned architecture designed to succeed where others might have failed in the past, RISC-V aims to learn from any potential past mistakes.
For this reason, RISC-V was designed as a modular ISA, as opposed to the traditional incremental ISAs. This means that a RISC-V implementation is composed of a mandatory base ISA and a number of ISA extensions, so that custom CPUs may be tailored to the application’s needs.
There are a number of companies manufacturing all variants of RISC-V cores in their microcontrollers, microprocessors, and SoCs. One example is SiFive, the first company to manufacture silicon-based on the RISC-V ISA. Their chips range from low-end microcontrollers all the way to high-performance SoCs.
Due to its open framework, the chipset will be very extensible, and we can see these microchips and SOCs populating our future markets.
- Mobile devices
- Smart home devices
- Automotive components
- Industrial Control Systems (ICS)
- … so many possibilities …
Qemu RISC-V emulation has already been available for some time.
Provided you have complied your Qemu emulator with the necessary flags to include the target_riscv32 and/or target_riscv64
Debian have a RISC-V virt image that you can download from here
Simply extract the contents of the zip file, and run the following command to launch an emulated virtual instance of RISC-V Debian. Note: we expose ssh and vnc, to obtain fast and efficient remote access. As the standard emulated display drivers are slow in comparision.
qemu-system-riscv64 -nographic -machine virt -smp 4 -m 2G \ -kernel dqib_riscv64-virt/kernel -initrd dqib_riscv64-virt/initrd \ -object rng-random,filename=/dev/urandom,id=rng0 -device virtio-rng-device,rng=rng0 \ -append "console=ttyS0 rw root=/dev/vda1" \ -device virtio-blk-device,drive=hd0 -drive file=dqib_riscv64-virt/image.qcow2,format=qcow2,id=hd0 \ -device virtio-net-device,netdev=usernet \ -netdev user,id=usernet,hostfwd=tcp::22222-:22,hostfwd=tcp::5901-:5901
Credentials, that you should change after first boot:
Dont forget to install a window manager, desktop and vnc server:
Now you’re free to play on RISV-V:
- General fun
- Vulnerability research
- Programming & low level coding development